Note: The job is a remote job and is open to candidates in USA. K2 Space Corporation is building the largest and highest-power satellites ever flown, aiming to unlock unprecedented performance levels across various orbits. They are seeking a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite systems, overseeing the full physical design flow and collaborating with various teams to ensure the success of their innovative projects.
Responsibilities
- Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off
- Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA)
- Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration
- Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools
- Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration
- Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards
- Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies
- Support chip bring-up and debug through close collaboration with post-silicon and test teams
- Support your product through production and spaceflight
Skills
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
- 10+ years of experience in ASIC physical design for high-performance SoCs
- Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens)
- Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation
- Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs
- Experience with advanced FinFET process nodes
- Prior experience managing or coordinating offshore/outsourced PD teams or vendors
- Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF)
- Excellent communication, leadership, and cross-functional collaboration skills
- Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team
- Exposure to radiation-hardened or space-qualified ASICs
- Experience with chip-package co-design or advanced packaging (2.5D/3D)
- Familiarity with physical design service vendor management or offshore collaboration
- Experience driving tapeouts through TSMC
- Experience with Gate-All-Around technologies
- Experience working in cross-functional, geographically distributed teams
Benefits
- Equity in the company
- Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
Company Overview
Making previously impossible missions possible It was founded in 2022, and is headquartered in Torrance, California, USA, with a workforce of 51-200 employees. Its website is https://www.k2space.com.